The present invention relates to semiconductor power device technology, and more particularly to charge balance techniques for semiconductor power devices.
A vertical semiconductor power device has a structure in which electrodes are arranged on two opposite planes. When the vertical power device is turned on, a drift current flows vertically in the device. When the vertical power device is turned off, due to a reverse bias voltage applied to the device, depletion regions extending in the horizontal and vertical directions are formed in the device. To obtain a high breakdown voltage, a drift layer disposed between the electrodes is formed of a material having high resistivity, and a thickness of the drift layer is increased. This, however, leads to an increase in the device on-resistance Rdson, which in turn reduces conductivity and the device switching speed, thereby degrading the performance of the device.
To address this issue, charge balance power devices with a drift layer comprising vertically extending n regions (n pillar) and p regions (p pillar) arranged in an alternating manner has been proposed. FIG. 1A is a layout diagram of such a device 100. Device 100 includes an active area 110 surrounded by a non-active perimeter region which includes a p ring 120 and an outer termination region 130. The perimeter p ring 120 has a rectangular shape with rounded corners. Termination region 130 may include similarly shaped alternating p and n rings, depending on the design. Active area 110 includes alternately arranged p pillars 110P and n pillars 110N extending vertically in the form of strips and terminating along the top and bottom at the perimeter ring 120. The physical structure of the alternating p and n pillars in the active area can be seen more clearly in FIG. 1B which shows a cross section view in array region 110 along line A-A′ in FIG. 1A.
The power device depicted in FIG. 1B is a conventional planar gate vertical MOSFET with a drift layer 16 comprising alternating p pillars 110P and n pillars 110N. Source metal 28 electrically contacts source regions 20 and well regions 18 along the topside, and drain metal 14 electrically contacts drain region 12 along the bottom-side of the device. When the device is turned on, a current path is formed through the alternating conductivity type drift layer 16. The doping concentration and physical dimensions of the n and p pillars are designed to obtain charge balance between adjacent pillars thereby ensuring that drift layer 16 is fully depleted when the device is in the off state.
Returning back to FIG. 1A, to achieve a high breakdown voltage, the quantity of n charges in the n pillars and the quantity of p charges in p pillars must be balanced in both the active area 110 and at the interface between the active area and the non-active perimeter region. However, achieving charge balance at all interface regions, particularly along the top and bottom interface regions where the p and n pillars terminate into perimeter ring 120, as well as in the corner regions where the n and p pillars have varying lengths, is difficult because of the change in geometry of the various regions. This is more clearly illustrated in FIG. 1C which shows an enlarged view of the upper left corner of power device 100 in FIG. 1A.
In FIG. 1C, a unit cell in active area 110 is marked as S1. Active p pillar 111 (which is divided into a left half portion 111-1 and a right half portion 111-2) and active p pillar 113 (which is divided into left half portion 113-1 and right half portion 113-2) are separated by an n pillar 112. The sum (Qp1+Qp2) of the quantity of p charges-Qp1 in the right half portion 111-2 of the active p pillar 111 and the quantity of p charges Qp2 in the left half portion 113-1 of the active p pillar 113 in unit cell S1 is equal to the quantity of n charges Qn1 in the active n pillar 112. An optimum breakdown voltage is thus achieved in all parts of active area 110 where such balance of charge is maintained.
As shown, the corner portion of the non-active perimeter region includes the perimeter p ring 120 and termination region 130 with n ring 131 and p ring 132 which are arranged in an alternating manner. Perimeter p ring 120 (which is divided into a lower half portion 121 and an upper half portion 122) and termination region p ring 132 (which is divided into lower half portion 132-1 and upper half portion 132-2) are separated by n ring 131. The sum (Qpt1+Qpe) of the quantity of p charges Qpt1 in the lower half portion 132-1 of p ring 132 and the quantity of p charges Qpe in the upper half portion 122 of ring 120 in unit cell S2 is equal to the quantity of n charges Qnt in n ring 131. An optimum breakdown voltage is thus achieved in all parts of the non-active perimeter region where such balance of charge is maintained.
However, because of geometrical limitations, the quantity of p charges and the quantity of n charges at the interface between the active area and the non-active perimeter region are unbalanced in many places. The absence of charge balance in these regions results in a deterioration of the breakdown characteristics of the device. Thus, there is a need for charge balance techniques which eliminate the prior art charge imbalance problems at the active area to non-active perimeter region interface, thereby leading to higher breakdown voltage ratings.